The present disclosure relates generally to path tracing and, more specifically, to combined path tracing in static timing analysis.
Calculating path delay in signal propagation within an integrated circuit (IC) can be done by analyzing a particular IC design using computer tools that estimate signal propagation delays throughout the IC in order to determine the maximum operating frequency of the IC. However, the signals may propagate to their destination through different paths, thus causing the signals to reach their destination at different times depending on the signal delay through each of the paths. Therefore, there exists an interest in finding out what the path delays are in the IC to determine if the application and operating frequency are appropriate for the design. Given the large amounts of registers, gates, buffers, wires, etc. in ICs common in current devices, the calculation, adjustment, and reporting of all possible paths require vast amounts of time and computer resources. It is in this context that embodiments of the invention arise.
For example, due to the increase in size and complexity of integrated circuits, it has become necessary to use sophisticated tools to verify timing constraints. Particularly, before the advent of Static Timing Analysis (STA), timing constraints were typically verified using simulation-based techniques. As the complexity of integrated circuits grew, using simulation-based techniques to verify timing constraints became impractical because of their long runtimes, low capacities, and incomplete analyses.
Unlike simulation-based techniques, STA verifies timing by computing bounds on delay values. The goal of static timing analysis (STA) is to determine the earliest and latest possible switching times of various signals within a digital circuit. STA can generally be performed at the transistor level or at the gate level, using pre-characterized library elements, or at higher levels of abstraction, for complex hierarchical chips.
Under certain circumstances, the approach described above can result in an overly pessimistic estimate of timing performance. One such overly pessimistic scenario occurs in the situation in which early and late propagation delays are different (e.g. to account for process variability), and both early and late mode signals involved in a timing test share a common part of their propagation paths (typically the clock). In such a scenario, while an exact value of propagation delay for the common propagation elements is unknown, it is typically impossible for such common delay elements to be operating at both early and late delay extremes simultaneously, and hence, slack computed using extremes of late data and early clock arrival times (or vice versa) at a test results in an overly pessimistic bound on circuit performance. This pessimism can be reduced, or even fully removed, by the technique of common path pessimism removal (CPPR). After such a technique is implemented, paths are then traced again to generate a timing report, thereby adding a large amount of additional processing.
Accordingly, there is a need for a system and a method for efficiently performing static timing analysis which is amenable to time consuming steps such as CPPR, traversing paths for identifying a set of critical paths, generating timing reports, and similar procedures.